32k x 8 3.3v static ram cy7c1399 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 march 25 , 1999 features ? single 3.3v power supply ? ideal for low-voltage cache memory applications ? high speed 12/15 ns ? low active power 255 mw (max.) ? low cmos standby power (l) 180 m w (max.), f=f max ? 2.0v data retention (l) 40 m w ? low-power alpha immune 6t cell ? plastic soj and tsop packaging functional description the cy7c1399 is a high-performance 3.3v cmos static ram organized as 32,768 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and three-state drivers. the device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. an active low write enable signal (we ) controls the writing/ reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the con- tents of the location addressed by the information on address pins is present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. the cy7c1399 is available in 28-pin standard 300-mil-wide soj and tsop type i packages. logic block diagram pin configurations c1399C1 c1399C2 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view soj 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 9 a 0 a 11 a 13 a 12 a 14 a 10 selection guide 7c1399C12 7c1399C15 7c1399C20 7c1399C25 7c1399C35 maximum access time (ns) 12 15 20 25 35 maximum operating current (ma) 60 55 50 45 40 maximum cmos standby current ( m a) 500 500 500 500 500 maximum cmos standby current ( m a) l50 50 50 50 50
cy7c1399 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. C65 c to +150 c ambient temperature with power applied ............................................. C55 c to +125 c supply voltage on v cc to relative gnd [1] .... C0.5v to +4.6v dc voltage applied to outputs in high z state [1] ....................................C0.5v to v cc + 0.5v dc input voltage [1] .................................C0.5v to v cc + 0.5v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma pin configuration 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 top view tsop 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 c1399C3 i/o 3 operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial C40 c to +85 c 3.3v 300 mv electrical characteristics over the operating range [1] 7c1399C12 7c1399C15 7c1399C20 parameter description test conditions min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3v 2.2 v cc +0.3v 2.2 v cc +0.3v v v il input low voltage C0.3 0.8 C0.3 0.8 C0.3 0.8 v i ix input load current C1 +1 C1 +1 C1 +1 m a i oz output leakage current gnd v i v cc , output disabled C5 +5 C5 +5 C5 +5 m a i os output short circuit current [2] v cc = max., v out = gnd C300 C300 C300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 60 55 50 ma i sb1 automatic ce power-down current ttl inputs max. v cc , ce 3 v ih , v in 3 v ih , or v in v il ,f = f max 5 5 5 ma l3 3 3 i sb2 automatic ce power-down current cmos inputs [3] max. v cc , ce 3 v cc C 0.3v, v in 3 v cc C 0.3v, or v in 0.3v, we 3 v cc C 0.3v or we 0.3v, f=f max 500 500 500 m a l50 50 50 notes: 1. minimum voltage is equal to C 2.0v for pulse durations of less than 20 ns. 2. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 3. device draws low standby current regardless of switching on the addresses.
cy7c1399 3 electrical characteristics over the operating range(continued) 7c1399C25 7c1399C35 parameter description test conditions min. max. min. max. unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3v 2.2 v cc +0.3v v v il input low voltage C0.3 0.8 C0.3 0.8 v i ix input load current C1 +1 C1 +1 m a i oz output leakage current gnd v i v cc , output disabled C5 +5 C5 +5 m a i os output short circuit current [2] v cc = max., v out = gnd C300 C300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 45 40 ma i sb1 automatic ce power-down current ttl inputs max. v cc , ce 3 v ih , v in 3 v ih , or v in v il , f = f max 5 5 ma l 3 3 ma i sb2 automatic ce power-down current cmos inputs [3] max. v cc , ce 3 v cc C0.3v, v in 3 v cc C 0.3v, or v in 0.3v, we 3 v cc C0.3v or we 0.3v, f=f max 500 500 m a l 50 50 m a capacitance [4] parameter description test conditions max. unit c in : addresses input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 5 pf c in : controls 6 pf c out output capacitance 6 pf ac test loads and waveforms note: 4. tested initially and after any design or process changes that may affect these parameters. 3.0v 3.3v output r1 317 w r2 351 w c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.73v equivalent to: thvenin equivalent all input pulses c1399C4 167 w
cy7c1399 4 switching characteristics over the operating range [5] 7c1399C12 7c1399C15 7c1399C20 7c1399C25 7c1399C35 parameter description min. max. min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 20 25 35 ns t aa address to data valid 12 15 20 25 35 ns t oha data hold from address change 3 3 3 3 3 ns t ace ce low to data valid 12 15 20 25 35 ns t doe oe low to data valid 5 6 7 8 10 ns t lzoe oe low to low z [6] 0 0 0 0 0 ns t hzoe oe high to high z [6, 7] 5 6 6 7 7 ns t lzce ce low to low z [6] 3 3 3 3 3 ns t hzce ce high to high z [6, 7] 6 7 7 8 8 ns t pu ce low to power-up 0 0 0 0 0 ns t pd ce high to power-down 12 15 20 25 35 ns write cycle [8, 9] t wc write cycle time 12 15 20 25 35 ns t sce ce low to write end 8 10 12 15 20 ns t aw address set-up to write end 8 10 12 15 20 ns t ha address hold from write end 0 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 0 ns t pwe we pulse width 8 10 12 15 20 ns t sd data set-up to write end 7 8 10 11 12 ns t hd data hold from write end 0 0 0 0 0 ns t hzwe we low to high z [8] 7 7 7 7 7 ns t lzwe we high to low z [6] 3 3 3 3 3 ns data retention characteristics (over the operating range) parameter description conditions min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc C 0.3v, v in > v cc C 0.3v or v in < 0.3v 200 m a l 20 m a t cdr [4] chip deselect to data retention time 0 ns t r [4] operation recovery time t rc ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and capacitance c l = 30 pf. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , t hzwe are specified with c l = 5 pf as in ac test loads. transition is measured 500 mv from steady state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that termina tes the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1399 5 data retention waveform c1399C5 3.0v 3.0v t cdr v dr 3 2v data retention mode t r ce v cc switching waveforms notes: 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. address data out previous data valid data valid t rc t aa t oha c1399C6 read cycle no. 1 [10, 11] 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance icc isb t hzoe t hzce t pd oe ce high v cc supply current c1399C7 read cycle no. 2 [11, 12]
cy7c1399 6 notes: 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 15. during this period, the i/os are in the output state and input signals shold not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe c1399C8 data in valid write cycle no. 1 (we controlled) [8, 13, 14] note 15 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce c1399C9 data in valid write cycle no. 2 (ce controlled) [8, 13, 14] data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe c1399C10 data in valid write cycle no. 3 (we controlled, oe low) [9, 14] note 15
cy7c1399 7 document #: 38C00222Cg truth table ce we oe input/output mode power h x x high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z deselect, output disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 12 cy7c1399C12vc v21 28-lead molded soj commercial cy7c1399lC12vc v21 28-lead molded soj cy7c1399C12zc z28 28-lead thin small outline package cy7c1399lC12zc z28 28-lead thin small outline package cy7c1399C12vi v21 28-lead molded soj industrial cy7c1399C12zi z28 28-lead thin small outline package 15 cy7c1399C15vc v21 28-lead molded soj commercial cy7c1399lC15vc v21 28-lead molded soj cy7c1399C15zc z28 28-lead thin small outline package cy7c1399lC15zc z28 28-lead thin small outline package cy7c1399C15vi v21 28-lead molded soj industrial cy7c1399C15zi z28 28-lead thin small outline package cy7c1399lC15zi z28 28-lead thin small outline package 20 cy7c1399C20vc v21 28-lead molded soj commercial cy7c1399lC20vc v21 28-lead molded soj cy7c1399C20zc z28 28-lead thin small outline package cy7c1399lC20zc z28 28-lead thin small outline package cy7c1399C20vi v21 28-lead molded soj industrial 25 cy7c1399C25vc v21 28-lead molded soj commercial cy7c1399lC25vc v21 28-lead molded soj cy7c1399C25zc z28 28-lead thin small outline package cy7c1399lC25zc z28 28-lead thin small outline package 35 cy7c1399C35vc v21 28-lead molded soj commercial cy7c1399lC35vc v21 28-lead molded soj cy7c1399C35zc z28 28-lead thin small outline package cy7c1399lC35zc z28 28-lead thin small outline package
cy7c1399 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 28-lead (300-mil) molded soj v21 51-85031-b 28-lead thin small outline package z28 51-85071-e
|
